Surface Traping in Silicon Nanowire Dual material engineered Cylindrical gate MOSFET



There is document - Surface Traping in Silicon Nanowire Dual material engineered Cylindrical gate MOSFET available here for reading and downloading. Use the download button below or simple online reader.
The file extension - PDF and ranks to the Presentations category.


204

views

on

Extension: PDF

Category:

Presentations

Pages: 9

Download: 49



Sharing files


Tags
Related

Comments
Log in to leave a message!

Description
In this paper, the effect of gate field screening by surface trap charges are studied using COMSOL 50 A nano wire dual material Cylindrical gate (DMCG) MOSFET is modeled and shift of turn on voltage due to the screening effect is computed It is shown that DMCG design increase the drain current enhancement However here the concept of work function difference also present in term of gate bias and comprehensive study of short channel effect of DMCG has been focused The objective of this paper is focus on Current vs Gate voltage, Energy Band diagram, CurrentDensity, electron and hole concentration and Electric field when MOSFET is turn on It is also examined that Cylindrical MOSFET the minimum surface potential in the channel reduces which resulting increasing in electron velocity and thereby improving carrier transport efficiency
Transcripts
   International Journal of Advanced Research in Technology, Engineering and Science (A Bimonthly Open Access Online  Journal) Volume2, Issue5, Sept-October, 2015ISSN:2349-7173(Online)   All Rights Reserved © 2015 IJARTES visit: wwwijartesorg  Page 1 Surface Traping in Silicon Nanowire Dual material engineered Cylindrical gate MOSFET Sanjiv Kumar Pal 1 , MrSubrat Kumar Pradhan 2 , Ms Swarna Prabha Jena 3 ,Ms Shanaz Aman 4 ABSRACT  In this paper, the effect of gate field screening by surface  trap charges are studied using COMSOL 50 A nano wire  dual material Cylindrical gate (DMCG) MOSFET is  modeled and shift of turn on voltage due to the screening effect is computed It is shown that DMCG design increase  the drain current enhancement However here the concept  of work function difference also present in term of gate bias  and comprehensive study of short channel effect of DMCG  has been focused The objective of this paper is focus on Current vs Gate voltage, Energy Band diagram, CurrentDensity, electron and hole concentration and  Electric field when MOSFET is turn on It is also examined  that Cylindrical MOSFET the minimum surface potential in  the channel reduces which resulting increasing in electron velocity and thereby improving carrier transport efficiency  Keywords: Dual Material Cylindrical Gate, Short Channel  Effect, TrapDensity, Energy Band Diagram 1 INTRODUCTION The silicon technology is spreading widely and the IT revolution that is now reshaping society This technology is increasing in every year such a manner that a chip size are continuously decreasing whether the speed of transistor increases which offer superior performance However the minimization in size of MOSFET lead to increase Short channel effect (SCE) [1-3] such a drain induced barrier lowering (DIBL), punch through,channel length modulation and threshold voltage roll off The controllability degrading of the gate voltage over drain current is due to the increasing charge sharing from drain/source region First Author Name:  Sanjiv Kumar Pal, Student,  MTech(VLSI Design),CUTM, Jatani, Odisha, India Second Author Name:  Subrat Kumar Pradhan, Asst Prof,  ECE Dept, CUTM, Jatani, Odisha, India Third Author Name:  Mrs Swarna Prabha Jena, Asst Prof,  ECE Dept, CUTM, Jatani, Odisha, India Four Author Name:  Mrs Shanaz Aman, Asst Prof, ECE  Dept, CUTM, Jatani, Odisha, India Scaling limitation is overcome by designing different structure of MOSFET such as Double gate[4],Pi-gate[5],triple gate[6] or Fin-shaped gate[7],Omega gate[8] and cylindrical/surrounded gate[9-14] have been proposed But only Dual material gate cylindrical/Surrounding MOSFET is the best structure which control the scaling limitation and increase device performance The most important features of this structure is that the gate completely surround the channel potential in more effective manner Due to this the short channel immunity is increase In DMG structure two metal gate having different work function is used The gate having higher work function is placed near the source terminal called as Control gate and the gate having lower work function is placed near the drain terminal called as screen gate Due to work function difference a potential step and electric field is arises in the channel region which increase carrier transport efficiency and suppress the short channel effects Decreasing the device dimension also reduce the voltage level and gate oxide thickness which increase the gate leakage current and thus the device performance is reduces Due to this an increase in static power consumption arises , which can hamper the circuit operation [8] To overcome the above limitations intensive stress has been made for the use of high K dielectrics as a gate insulator in lieu of SiO 2  to prevent direct tunneling leakage current However, the studies illustrated thatsupersedingSiO 2 with high K dielectrics reduces the device performance due to the increased fringing fields from the gate to the source/drain regions, which decrease the control of gate over the channel Extremely thin layer of interfacial oxide is used as a coating reducesthe interfacetrapdensity thus increasing the device performance [15] In this work a 2-D asymmetric model of DMG cylindrical MOSFET is examine The model was verified by comparing the analytical result using COMSOL 50   International Journal of Advanced Research in Technology, Engineering and Science (A Bimonthly Open Access Online  Journal) Volume2, Issue5, Sept-October, 2015ISSN:2349-7173(Online)   All Rights Reserved © 2015 IJARTES visit: wwwijartesorg  Page 2 2 Model derivation 21 Device structure The following Fig1 is a 3-D structure of DMCG n- channel MOSFET The device contain two gate materials (M1 and M2) with different work functions ( Φ M1 and Φ M2 ) The two gate material length L 1  and L 2  are uniting to form the gate terminalwith total gate length define as L=L 1 + L 2 The gate material are chosen such that ( Φ M1 > Φ M2 ) the material with higher work function kept near the source end called as “ Control gate ” and the material with lower work function kept near the drain end called as “ Screen gate ” For p-channel MOSFET the gate having lower work function is used as Control gate and higher work function is used as Screen gate Fig1 3-D structure of a dual material cylindrical gate MOSFET Fig2Side view of the dual material cylindrical surrounding gate MOSFET   International Journal of Advanced Research in Technology, Engineering and Science (A Bimonthly Open Access Online  Journal) Volume2, Issue5, Sept-October, 2015ISSN:2349-7173(Online)   All Rights Reserved © 2015 IJARTES visit: wwwijartesorg  Page 3 Here the two gate metals Gold (Au) and Cadmium (Cd) having work function 48eV and 40eV are used as gate terminal respectively The Gold metal is used as Control gate whereas the Cadmium metal is used as Screen gate The p-type channel doping concentration is N a =1X10 17 cm -3 whereas the n +  drain and source concentration is N D =1X10 20 cm -3 with an abrupt doping profile at the drain and source to channel edgesSiO 2  is chosen as gate oxide material with permittivity 0 39 ε  where 0 ε   is the permittivity of the free space and thickness of about 12nmThe radius of the channel is R=10nm The device parameters are taken according to the International Technology Roadmap for semiconductors 2009 version for low operating power applications The surface traping density are 1X10 16  cm -2  and 5X10 16  cm -2   Let the influence of charge carrier in the channel is uniform which can be neglected The trap charge carrier in the channel is fixed The 2-D Poisson’s equationbefore the strong inversion is [16] 222 1(())((,))(1)  ASi qN r z r zr r r z z φ φ ε  ∂ ∂ ∂   + =   ∂ ∂ ∂    Where  A  N  is the acceptor doping concentration for the Silicon (cm -3 ), Si ε   is the relative permittivity of the Silicon ( 0 39 ε  ),q is the charge of electron, (,) r z φ   is the 2-D potential distribution in the channel r is the radius of the MOSFET channel The potential distribution of the silicon is considered as parabolic profile in the radial direction [18] and it is written as 2012 (,)(2) r z a a r a r  φ   = + +  Where a 0 , a 1 and a 2  are the function of z The device is fabricated with two gate having different work function To obtained the surface potential of the region the Poisson’s equation is solved by boundary condition [18]The surface potential for the two gate region is obtained as 221112 ()() S S  d zk zdz φ φ β  − = for 1 0(3)  z L ≤ ≤  And 222222 ()() S S  d zk zdz φ φ β  − = for 112 (4)  L z L L ≤ ≤ +  Where 1 S  φ   =The surface potential under the gate near the source 2 S  φ  = The surface potential under the gate near the drain ( ) 2 (5)  Ags FBSi qN k V V   β ε  = − −   FB V  =Flat band voltage 2 2(6) oxSi C k  R ε  =  R=Radius of the Silicon channel (7)ln1 oxoxoxeff  C t  R R ε  =    +        oxeff  t  =Thickness of silicon oxide 1122 (8) oxeff  t t t  ε ε  = +   1 t  =thickness if the SiO 2 layer 2 t  = thickness if the High k- layer By solving the equation (3) and (4) the following solution for the surface potential for each section is obtained as, 112 ()exp()exp() S   z A kz B kzk   β φ   = + − − for 1 0(9)  z L ≤ ≤  And 222 ()exp()exp() S   z C kz D kzk   β φ   = + − − for 112 ()(10)  L z L L ≤ ≤ +